How 5 Carbon Atoms Could Save Samsung's Foundry Bet

The problem no one talks about until it’s too late

Every generation of Moore’s Law shrinks transistors. But the wires connecting them—interconnects—have become the quiet bottleneck. As copper traces narrow below 10 nanometers, their electrical resistance spikes due to quantum confinement and surface scattering. At the 2nm node, copper may simply stop being viable.

Ruthenium is the industry’s candidate to replace it. Lower resistivity in thin films, better scalability, no electromigration issues. But ruthenium has its own flaw: when deposited as a thin film on amorphous insulating substrates—the default in real chips—its crystalline grains stay small and randomly oriented. Small grains mean more grain boundaries. More grain boundaries mean more electron scattering. More scattering means higher resistance. The very material chosen to solve the interconnect crisis was introducing a new one.

Five atoms changed everything

A team from GIST, Samsung’s SAIT lab, and MIT found the fix, and it required barely anything. They published the work in Science on August 22, 2026. The key: adding approximately 0.48 atomic percent carbon—roughly five carbon atoms per thousand ruthenium atoms—to the deposition process, followed by a 450°C heat treatment.

The mechanism is elegant. During annealing, carbon atoms migrate to the grain boundaries where adjacent Ru crystals meet. They form carbon-rich regions that then rapidly outgas as CO or CO₂, leaving behind temporary voids—what the researchers call “free volume.” These transient spaces give neighboring grains the mobility to grow and rotate into alignment. The carbon is a promoter, not a permanent dopant. It facilitates, then leaves.

The results are stark. Average grain size jumped from 13 nanometers to 91.7 nanometers—nearly seven times larger. The degree of crystalline orientation hit 99.3%. An 8nm-thick Ru film dropped to 11.2 microhm-centimeters of resistivity, 29% lower than untreated Ru. And when the researchers built actual ultrafine wiring structures mimicking production conditions, interconnect resistance fell by 45.4%.

Why 45% matters more than the number sounds

Semiconductor interconnect resistance has been climbing exponentially as nodes shrink. A 45% reduction isn’t incremental—it approaches an order-of-magnitude shift in the same parameter that has been deteriorating for years. For a technology node where every picosecond of signal delay and every milliwatt of dynamic power counts, this kind of improvement changes the feasibility envelope.

The team also demonstrated uniformity in demanding geometries: a 12nm Ru coating inside a trench with a 33:1 aspect ratio achieved 99.1% coverage on both sidewalls and the bottom, with crystalline orientation preserved throughout. That’s the kind of conformality foundry process engineers spend years chasing.

The players behind the paper

The Korean institutional weight behind this is notable. GIST (Gwangju Institute of Science and Technology) is a lean, research-intensive university that punches far above its enrollment size. Dr. Jo Yong-ryoon, the lead postdoctoral researcher, conducted the real-time heating TEM observations that allowed the team to watch grain growth and reorientation happen live inside the microscope. That level of in-situ characterization is not routine.

Samsung’s SAIT—formerly the Samsung Advanced Institute of Technology—contributed co-first author Dr. Im Yong-cheol as corresponding author, along with seven additional co-authors. The involvement of MIT’s Kim Ji-hwan as co-author adds a US institutional anchor. The three-party structure isn’t ceremonial: it reflects the division of labor, with GIST providing the microscopy and materials insight, Samsung providing the device-relevant validation, and MIT likely contributing the growth modeling framework.

What this means for the foundry race

Samsung has been trailing TSMC in leading-edge foundry volume production. The 2nm node is supposed to be Samsung’s catch-up moment, and interconnect performance is a make-or-break variable. Copper-based schemes struggle at this scale; ruthenium has been the leading alternative but has underperformed on resistance. This work directly addresses the gap.

The timeline for adoption matters. The paper describes laboratory-scale validation. Translating a carbon-promoted deposition-and-anneal sequence into a high-volume fab requires qualifying the process for contamination control, throughput, and yield. The good news: the heat treatment temperature of 450°C is modest by fab standards. The unknown: whether the carbon outgassing step introduces particle or contamination risks that would need new scrubbing or exhaust handling.

GIST’s stated follow-on plan—to extend the “carbon promoter” concept to other metals and dopants—suggests the group sees this as a generalizable strategy, not a one-off fix. If that trajectory holds, the research opens a whole class of grain-engineering approaches for next-generation interconnects.

Who wins, who loses, and what happens next

Samsung wins if this reaches pilot production ahead of TSMC’s equivalent interconnect solution. TSMC is undoubtedly working on ruthenium or alternative low-resistance interconnect schemes; the difference will be who ships first with a manufacturable process. The publication in Science gives Samsung a timing advantage in terms of intellectual priority, but priority in journals doesn’t equal priority on the fab floor.

The broader semiconductor supply chain stands to gain too. Any foundry adopting ruthenium interconnects with improved resistance will see lower RC delay and reduced power dissipation—two of the three variables that determine whether a node actually delivers on its performance promises.

For Korea’s science policy ecosystem, this is a validation of the GIST model: a government-supported research institute producing work that feeds directly into the capabilities of the country’s largest industrial player. The $5.5 million Emerson NI software donation GIST received earlier in 2026, and its January 2026 non-destructive wafer inspection work, suggest a broader push to build instrumentation depth that can feed results like this.

The 2nm era doesn’t care about publications. It cares about which process makes it through lithography, deposition, etch, and yield testing first. This paper moves the materials case forward. The next chapter—fab integration—hasn’t been written yet.