Koreans Are Reallocating 30% of DRAM Factories to AI Memory

The Quiet Reallocation That Could Reshape Consumer Tech

Next year, nearly a third of the world’s DRAM wafer production capacity will be devoted to high-bandwidth memory — and most of that capacity is coming out of products you actually use. PC and smartphone memory supply is about to feel it.

Kim Tae-woo, vice president of Samsung Electronics’ memory business division, told Reuters that HBM will consume roughly 30% of total DRAM industry wafer capacity by next year, up from about 20% today. That is not a forecasting exercise from a third-party research shop. It is a statement from the person who sets Samsung’s production strategy for the single biggest DRAM manufacturer on earth, which controls about 40% of the global market.

The implication is direct: every HBM unit Samsung and SK Hynix prioritize is a DRAM chip for your phone or laptop that does not get built on the same equipment. Fab lines in Pyeongtaek and Hwasung that previously ran consumer memory now carry stacked HBM wafers. The physical infrastructure does not easily switch back.

Why HBM Eats More Than It Should

HBM is not just another type of DRAM. It requires stacking memory dies vertically — eight, twelve, possibly more layers — and each individual die occupies more silicon area than a standard DRAM chip designed for the same bit capacity. The result is a fundamentally less wafer-efficient product.

According to TrendForce, HBM will use 30% of global DRAM wafers next year but account for only about 13% of total bit production volume. That gap between wafer share and bit share is where the squeeze lives. The same factory floor, the same number of wafers, now produces far fewer consumer memory bits.

The problem compounds because AI servers need both HBM and ordinary DDR5. GPUs carry HBM alongside their processors, while CPUs in the same machines require large DDR5 capacities. As data centers expand, demand for both rises together — pulling more wafers away from the consumer segment on both sides. A single AI training cluster can consume tens of thousands of HBM packages and hundreds of DDR5 modules, a demand profile that would have been unthinkable five years ago.

Prices Already Moving

The market is responding before the shortage fully arrives. TrendForce projects that HBM’s average selling price will surge 121% next year, driven by the rising sales mix of expensive HBM4 and persistent supply constraints. That cost pressure is already creating second-order effects among AI chip designers.

NVIDIA and other accelerator makers are reportedly considering reducing HBM capacity per chip. The logic is practical: an eight-stack HBM package can produce more units from the same number of DRAM dies than a twelve-stack design. If you can fit the required bandwidth with fewer layers, you get more chips out of each wafer. The tradeoff is raw capacity per GPU — a decision that could slow the next generation of model training speeds if memory supply remains tight.

Memory module makers face a different kind of pressure. Companies that assemble and distribute DRAM for consumer and enterprise systems are watching their input costs shift upward as foundry allocation tilts toward HBM. Some are locking in long-term supply agreements at premium prices; others are scrambling to find alternative sourcing from smaller producers who lack the volume to meet growing demand.

It is a subtle signal of how much leverage memory suppliers now hold in the AI hardware chain.

The Korean Duel Is Tightening Fast

The more immediate story, though, is the race between Samsung and SK Hynix for HBM dominance.

For years, SK Hynix held a commanding lead. It was first to volume production of HBM3E and secured deep ties with NVIDIA, the dominant AI chipmaker. By the first quarter of this year, SK Hynix held 58% of HBM revenue share. Samsung trailed at 21%.

By the second quarter, the gap had closed sharply. SK Hynix fell to 50%. Samsung rose to 33%, according to Counterpoint Research. Several market analysts and investment banks now project Samsung will overtake SK Hynix in HBM bit shipment volume next year. UBS estimates Samsung at 41% versus SK Hynix at 39%.

The shift reflects Samsung’s aggressive push into HBM4. The company is using its own 1C-class DRAM dies and a logic base die fabricated on its proprietary 4-nanometer process, aiming to ramp production faster than anyone expected. Samsung’s approach relies on vertical integration — controlling both the memory dies and the underlying logic architecture — which reduces dependency on external foundry partners and shortens qualification timelines.

SK Hynix is not standing still. The company says its HBM4 yields and quality have already approached those of HBM3E, and it is expanding production capacity as planned. HBM is not a market where simply allocating more wafers guarantees victory. Customer qualification cycles are long, yield curves matter enormously, and established supply relationships carry real weight — all areas where SK Hynix has accumulated advantages over years of first-mover execution. NVIDIA has been openly cautious about switching suppliers mid-generation, and those relationships are deeply entrenched.

What This Means for the Rest of the Industry

The realignment of DRAM capacity toward HBM creates a structural tension that will define the memory market through at least 2027.

For consumers, the risk is straightforward: if wafer allocation to PC and smartphone DRAM shrinks meaningfully, prices for those components will rise. The effect may be gradual rather than sudden, but it is real. Data center growth is consuming the supply curve that consumer electronics once relied on. Laptop and smartphone manufacturers who source DRAM on spot markets will feel the pain first, while larger OEMs with contractual agreements may weather the disruption a bit longer — at higher cost.

The enterprise storage segment is also watching closely. Data center servers that rely on high-density DRAM for caching and workload acceleration will compete with AI infrastructure for the same wafer allocation. Some system integrators are already exploring alternative memory architectures or redesigning server architectures to use less DRAM per node — moves that could reshape how AI-adjacent infrastructure is built.

For competitors, the window is narrowing. TSMC and Micron are closing the HBM gap, but Samsung and SK Hynix are investing with the urgency of companies that know their market position depends on this transition. TSMC has begun offering HBM packaging services through its CoWoS platform, giving memory fabless competitors an alternative route to market. Micron has announced plans to bring HBM4 online this year, but its first-generation entry lacks the ecosystem relationships that SK Hynix and Samsung have cultivated over half a decade.

The one who fails to capture HBM scale risks losing influence over the entire AI infrastructure supply chain. Memory is no longer a commodity behind the scenes — it is a strategic bottleneck at the center of the AI arms race.

For AI manufacturers, the memory squeeze is a cost problem with no easy fix. Reducing HBM stack height saves wafers but constrains performance. Paying more for HBM margins into the memory makers’ coffers. Building alternative memory architectures is possible but slow. Every path forward involves tradeoffs that were not necessary even eighteen months ago.

The 30% figure is not just a production statistic. It is a mirror of where the semiconductor industry’s center of gravity has shifted — from the devices people carry to the machines that think. And the Korean memory duopoly, for all its internal competition, now sits at the fulcrum of that transition. Whatever happens in those fabs in Pyeongtaek and Hwasung will echo through every corner of the tech economy for years to come.