Samsung's High-NA Gamble Could Flip the Memory Chip Pecking Order

The Real Story Behind the High-NA EUV Race

When Samsung announced it targets High-NA EUV equipment by 2028, the headline wasn’t just another corporate timeline. It was a declaration that Samsung intends to lead the next generation of memory chip manufacturing — a domain where it has historically dominated but recently faltered in process-node leadership.

Three companies are now racing to use ASML’s most expensive machine ever built. Intel has already started using High-NA EUV on select layers of its 18A process, delivering chips this year. TSMC said it will begin in 2030. Samsung is aiming for 2028 — two years ahead of its closest foundry rival.

The stakes are measured in hundreds of millions of euros per system. Each High-NA EUV tool costs up to €350 million, more than double the price of the current-generation EUV machines that cost roughly €200 million each. A single unit is nearly four times the price of an F-35 fighter jet. And this is only the lithography tool — it is not a complete fab investment.

Why Samsung’s Timeline Is the Disturbing Part

Samsung’s ambition to run High-NA EUV for DRAM production by 2028 is notable because DRAM is not where the industry’s immediate attention is focused. The AI chip narrative has been dominated by logic-process competition — TSMC’s leading-edge nodes, Intel’s long-awaited comeback with 18A, and the relentless push for smaller transistors in GPUs and custom accelerators.

But DRAM is undergoing its own transformation. High-bandwidth memory, or HBM, which is essential for every major AI training chip, is a DRAM product. Samsung’s move suggests it sees High-NA EUV not merely as a logic-node upgrade path but as a lever to accelerate the density and yield improvements needed for next-generation memory that AI servers demand.

If Samsung succeeds in deploying High-NA EUV for DRAM by 2028, it could regain a structural advantage in the memory segment that feeds directly into the AI compute supply chain. That would give it leverage beyond the foundry business — something Samsung has lacked while Intel and TSMC have fought over logic-node supremacy.

Intel’s Early Lead Is Real but Narrow

Intel received its first High-NA EUV tools in 2024 and began using them on parts of the 18A chip layer stack this year. That gives Intel roughly a two-year head start over Samsung and a six-year head start over TSMC. In semiconductor manufacturing, two years is an eternity.

But Intel’s advantage comes with important caveats. The company’s earlier struggles with process delays — particularly at its 10-nanometer and 7-nanometer nodes, which fed directly into the decision to adopt High-NA EUV aggressively — mean Intel’s first-mover status was born partly from necessity rather than pure strategy. The 18A process itself has yet to prove itself at volume in the competitive foundry market.

Intel is using High-NA EUV selectively, on “some layers” of 18A, according to Nikkei Asia. That is not the same as a full process migration. The question is whether selective use of the most expensive equipment in the world will translate into a meaningful performance or efficiency advantage large enough to justify the cost.

TSMC’s Pause Was Always a Calculation

TSMC’s 2030 timeline is not a sign of weakness. It is a rational response to the economics of High-NA EUV. When TSMC’s leadership called the existing EUV tools too costly to deploy broadly back in 2019, the market read that as caution. In hindsight, it was calibration.

TSMC’s foundry business rests on scale and yield stability across thousands of designs. High-NA EUV is unproven at volume, enormously expensive, and demands new process integration work. TSMC appears to be waiting for the technology to mature and for the cost curve to descend before committing its customer base to a process node that has never been demonstrated in mass production.

That strategy protects TSMC’s margins. But it also means ceding the narrative — and potentially some of the earliest design wins at the bleeding edge — to competitors willing to absorb the risk.

The Memory Chip Hierarchy Could Shift

The most consequential implication of Samsung’s 2028 target is what it signals about where value is migrating in the semiconductor supply chain. For decades, the hierarchy was clear: TSMC leads in advanced logic, Samsung leads in memory, and Intel straddled both with varying success.

AI is blurring those lines. Every major AI accelerator — Nvidia’s H100 and B100 series, Google’s TPUs, Amazon’s Trainium — depends on HBM, which Samsung produces. If Samsung can use High-NA EUV to push HBM density higher and yield faster than competitors can match, it gains strategic leverage over the very chips driving the AI boom.

That is the quiet shift the industry may be underestimating. The public debate centers on logic nodes and transistor counts. But the memory side of the equation — where Samsung holds the strongest position — is where the next round of competitive pressure will land first.

Who Wins and Who Loses

Samsung wins if its 2028 target is achievable. It regains narrative dominance, strengthens its memory business with a technology edge, and creates a potential bottleneck for competitors who rely on HBM supply. It also signals to customers that Samsung is willing to absorb enormous capital expenditure for strategic positioning.

Intel’s early use of High-NA EUV gives it a credibility boost in its foundry ambitions, but only if 18A delivers sustained yield and performance. If the process stumbles, the expensive equipment becomes a liability rather than an asset.

TSMC’s slower timeline is strategically defensible but reputationally costly. In an industry where first impressions shape customer decisions, being last to deploy the most advanced tool matters — even if the tool itself is not yet proven at scale.

ASML benefits regardless. The company’s monopoly on High-NA EUV means every sale goes directly to its bottom line, and three major fabs committing to the technology validates the entire roadmap.

What Comes Next

The semiconductor industry is entering a phase where the gap between the most advanced equipment and everything else is widening further. China’s SMIC cannot purchase High-NA EUV tools under current US and Dutch export controls. Even access to current-generation EUV is restricted. That restriction isolates China from the leading edge not just today but for the foreseeable future.

For Samsung, Intel, and TSMC, the next 18 months will be critical. Intel is already running High-NA EUV on limited layers. Samsung must demonstrate that its 2028 target is real and not aspirational. TSMC will face increasing pressure from customers who want assurance that its later timeline does not reflect technological hesitation.

The price of admission to the next generation of chip manufacturing is now over €350 million per tool. That is not a barrier — it is a filter. Only companies that can absorb that cost and still deliver competitive products will remain in the race. Everyone else is already behind.