Samsung and SK Hynix Are Racing Beyond HBM — And It Changes Everything

The Real Story Behind the HBM4E Show

Samsung and SK Hynix stood side by side at SEDEX 2026 in Seoul and unveiled the same headline product — HBM4E, the seventh generation of high-bandwidth memory. But reading the press releases would miss the point. Both companies used the HBM4E launch as a staging ground for something larger: a fundamental restructuring of how memory sits inside an AI system.

The bandwidth numbers are impressive. Samsung’s HBM4E pushes 16 gigabits per second per pin, up from 14 Gbps on HBM4, with a maximum throughput of 3.6 terabytes per second. A 12-layer stack holds 48 gigabytes, a jump of more than 30 percent over the previous generation. SK Hynix matched the 16 Gbps figure and claimed a 20 percent improvement in energy efficiency. These are incremental gains along a known curve.

The architectures announced alongside HBM4E are not.

zHBM Changes the Geometry of the Bottleneck

Samsung showed a model of zHBM — a three-dimensional memory structure in which the HBM stack sits directly on top of the GPU die rather than beside it on the interposer. This is not a minor packaging tweak. It compresses the physical distance data must travel between compute and memory, which is precisely where the AI training bottleneck lives.

Every generation of HBM has chased more bandwidth. Each improvement also raises power density and thermal constraints on the package. Stacking memory on the processor die rather than alongside it shifts the engineering problem from the board level to the Fab level, where Samsung has been building its foundry and advanced packaging capabilities for years. That alignment of strategy and infrastructure matters more than any single product spec.

Samsung also exhibited LPDDR-PIM, a processing-in-memory approach that performs some computation inside the memory die itself. The logic is simple and hard to ignore: if you can execute a portion of the AI workload inside the memory stack, you reduce the number of round trips between memory and processor, which saves both time and energy. The company positioned this for edge AI devices, where power budgets are tighter and every watt counts.

HBF Introduces a New Layer Between HBM and SSD

SK Hynix took a different architectural route. Instead of reorganizing the GPU-package geometry, it proposed inserting a new memory tier between HBM and NAND flash storage. The company calls it HBF — high-bandwidth flash — and claims it can deliver roughly ten times the capacity of conventional HBM while retaining high data throughput.

Current AI servers already layer multiple memory technologies: HBM closest to the GPU, then DRAM, then SSD storage. Each hop between these tiers introduces latency. SK Hynix’s vision is to fill the gap between HBM’s speed and NAND’s capacity with a medium that is faster than flash but far more capacious than HBM. Whether that medium materializes as a new kind of NAND, a phase-change material, or something else entirely remains unclear. What is clear is that the idea reflects a growing conviction across the industry: bandwidth alone does not solve the AI memory crisis.

The broader implication is that the memory hierarchy for AI is about to expand from three layers to four or five, and whoever defines the interfaces between those layers will capture significant value.

The 2030 Multiplier Is the Real Driver

An Hyun SK Hynix’s vice chairman of development predicted at the event that AI infrastructure performance will grow roughly twenty-fold by 2030 compared with today. That is a strikingly specific number from a company that does not typically make forward-looking statements of this magnitude at trade shows. Whether he meant compute throughput, total data moved, or system-level capability was not specified.

The direction is unambiguous regardless. Existing HBM roadmaps chase linear improvements in bandwidth and layer count. The volume of data an AI system must shuffle between memory and processor scales faster than memory can keep up on current trajectories. Both Korean companies appear to be betting that architectural innovation — stacking, in-memory computation, new memory tiers — will close the gap that pure process-node improvements cannot.

This is a bet against the assumption that memory will continue to scale along the same curve it has followed since HBM2. It is also a bet that Korea can leverage its dominant position in DRAM manufacturing to reshape the entire AI memory architecture, not just supply components inside someone else’s design.

Packaging Is the New Frontier

What received less attention at the show but may matter most is the packaging dimension. Samsung displayed its 2.3D Cube-E and 3D Cube-H advanced packaging technologies alongside the HBM4E base die, which is manufactured on a 4-nanometer foundry process. The message is that next-generation memory competitiveness depends on more than cell density. It depends on how tightly memory, logic, and interconnect can be integrated.

SK Hynix emphasized its partnership with Nvidia, displaying a HBM wafer signed by Jensen Huang alongside samples validated for Nvidia’s Vera Rubin platform. The subtext is that access to leading GPU architectures determines which memory suppliers move from component vendors to system co-developers. The companies that embed themselves into GPU design cycles early will shape the memory hierarchy for the next generation of AI hardware.

Who Wins, Who Loses

Samsung’s strategy leans on vertical integration — it controls memory manufacturing, foundry logic, and packaging under one roof. That structure lets it offer customers a coordinated stack from silicon to system. The risk is that each layer is capital-intensive and the timelines for zHBM and PIM commercialization remain uncertain.

SK Hynix is pursuing a different path: specializing in memory-tier innovation while deepening co-development relationships with GPU leaders. The HBF concept could open a new market segment if it reaches production. The risk is that it depends on a customer or standard body adopting an entirely new memory layer into an established hierarchy — a tall order when incumbent suppliers already have locked-in designs.

Intel and TSMC face a common problem. Neither manufactures the DRAM that powers AI accelerators, and both are competing to define how memory integrates with their foundry and packaging offerings. If Samsung and SK Hynix succeed in establishing new memory hierarchies, they gain leverage over the system architects who depend on their products.

Western coverage of the AI chip war focuses almost exclusively on GPU performance and training clusters. The Korean moves at SEDEX signal that the next constraint may not be compute at all — it may be how efficiently a system moves data between the layers that store it.

What Happens Next

Both zHBM and HBF are still in development. Commercial availability, customer adoption, and yield rates are unknown. The companies are planting flags now, before the industry standards solidify around whatever architecture wins. That is a recognizable pattern in semiconductor competition: announce the roadmap early, lock in design wins, and let the manufacturing catch up.

The HBM4E product cycle itself will be the first test. Samsung has already shipped 12-layer samples and plans 8-layer and 16-layer variants. SK Hynix is in validation with major customers. Whichever company secures the earliest volume design wins on next-generation AI accelerators will set the reference architecture that others follow.

The memory bottleneck in AI is not shrinking. It is shifting from a question of how fast data moves to a question of where data lives relative to the processor that needs it. Samsung and SK Hynix are betting that the answer to that question will determine who profits from the next decade of AI infrastructure buildout.