The EUV Arms Race That Could Redraw the Chip World

The Clock Is Ticking Louder

Samsung has moved its High NA EUV adoption date to 2028. TSMC is targeting 2030. Both are compressing timelines that were never comfortable in the first place. And both are now betting their next-generation chip leadership on equipment that costs roughly $400 million per unit — with only one company on Earth capable of building it.

What this looks like on the surface is a routine upgrade cycle. What it actually represents is a race against a narrowing window of technological supremacy, one that Samsung and TSMC now recognize is closing faster than anyone anticipated.

The Real Driver: China, Not Just AI

The Bloomberg report framing this story emphasizes AI chip demand. That is not wrong. But it is incomplete. The more consequential force at work is China’s relentless push into advanced semiconductor manufacturing and the West’s increasingly aggressive containment strategy.

High NA EUV tools are not merely incremental improvements over existing EUV lithography. They represent a fundamental step change — higher numerical aperture means finer circuit patterns, fewer曝光 passes, and the ability to shrink transistor dimensions in ways that conventional EUV simply cannot achieve. For a few years, this gap was wide enough that even if China acquired current-generation EUV tools, they would remain a generation behind. That buffer is shrinking.

Intel, incidentally, already operates High NA EUV equipment. Its participation in the 12-inch photomask development alongside Samsung, TSMC, and ASML is not incidental — it is a signal that the Foundry 2.0 strategy at Intel depends on this technology, and that American fabs are treated differently from their Asian counterparts when it comes to equipment access.

The 12-Inch Gamble

Here is where the story gets interesting. Samsung and TSMC are not just buying ASML’s machines. They are jointly developing 12-inch photomasks to replace the 6-inch standard that the industry has used for decades. This is a massive technical undertaking — photomasks are the stencils through which circuit patterns are projected onto wafers, and doubling their size introduces enormous complexity in defect control, alignment, and throughput.

ASML’s own CTO, Marco Peters, called the shift “an important milestone” toward High NA EUV mass production. The company projects a 40 percent increase in production throughput once 12-inch masks are deployed. Forty percent. That is not a marginal improvement. That is the difference between making High NA EUV economically viable at volume and leaving it as a niche tool for the most extreme chip designs.

TSMC was reportedly hesitant about High NA EUV adoption for exactly the reason you would expect — the cost per unit was hard to justify when yield and throughput were still uncertain. Now the calculus has flipped. AI demand has made the economics clearer, and TSMC CEO C.C. Wei’s comments about overcoming technical barriers before they become cost barriers suggest the foundry giant is treating this as a now-or-never investment.

Who Wins, Who Loses

ASML wins. It is the only company in the world that can produce EUV lithography equipment, and TSMC alone accounts for roughly 16 percent of ASML’s total revenue. Every High NA EUV tool sold to TSMC and Samsung is revenue at the highest margin tier of ASML’s portfolio, and the 12-inch mask partnership locks those customers deeper into ASML’s ecosystem for years to come.

Intel wins too — not because it is leading the pack (it is trailing TSMC in node density), but because its early access to High NA EUV equipment and inclusion in the mask development consortium gives it a lifeline for its own foundry ambitions.

Samsung and TSMC win conditionally. They secure their positions at the cutting edge for the next several years. But they are also taking on enormous capital expenditure risk. If AI demand softens, or if chip design evolves in a direction that reduces the value of smaller transistors, these tools could become stranded assets worth $400 million each.

China loses the most. Every year that passes with High NA EUV locked behind export controls is a year China spends catching up on older nodes while being blocked from the most advanced ones. That containment strategy is working — but it is also accelerating China’s incentive to develop alternative lithography pathways, including the deep ultraviolet (DUV) multi-patterning approaches Chinese fabs have been pursuing with increasing sophistication.

What Happens Next

The timeline matters. Samsung’s 2028 target means High NA EUV production volumes will begin flowing within three years. TSMC’s 2030 date gives it another two years of process refinement. That two-year gap could be decisive in the competitive positioning of leading-edge logic chips — particularly AI accelerators, where TSMC currently dominates.

The 12-inch photomask development is the other variable. If the transition proceeds smoothly and ASML delivers on its 40 percent throughput improvement claim, High NA EUV becomes a scalable production technology rather than a laboratory curiosity. If delays mount — and mask transitions almost always do — the economics could sour before the technology proves itself.

There is also the geopolitical dimension that rarely makes headlines but shapes every decision in this equation. US export controls on EUV equipment to China are tightening, not loosening. That means ASML’s customer base for High NA EUV will remain confined to the US alliance — primarily TSMC in Taiwan, Samsung in South Korea, and Intel in the United States. No Chinese fab will see this equipment. No Chinese fab will be able to produce the most advanced chips for the foreseeable future.

That containment has a second-order consequence: it pushes China to invest even more aggressively in alternative routes — DUV multi-patterning, chiplet architectures that sidestep single-chip complexity, and potentially novel lithography approaches that could one day erode ASML’s monopoly.

The High NA EUV race is not just about who prints the smallest transistors. It is about who controls the tools that make those transistors possible, and for how long that control remains uncontested.