TSMC's Backside Power Play Sets Up Samsung's Darkest Foundry Hour

The wafer just flipped over

TSMC has completed development and verification of its A16 process — a 1.6-nanometer node that does something the rest of the industry is still theorizing about. It routes electrical power through the back side of the silicon wafer instead of the front.

The result, according to the company, is 8 to 10 percent faster switching at the same voltage, or 15 to 20 percent less power consumed at the same speed, compared with TSMC’s current leading node, N2P. Chip integration density also improves by up to 10 percent.

The difference may sound incremental on paper. It is not.

The physics problem that everyone forgot

Semiconductor scaling has always been a war against crowding. As transistors shrink, you need more power and more signal lines packed into the same area. The congestion creates two problems: voltage drops along the power rails, and electromagnetic interference between data and power pathways. These effects compound as nodes get smaller.

By the time you reach single-digit nanometers, the front side of a wafer is essentially the most expensive real estate on Earth. Every square micrometer that carries a power rail is a square micrometer that cannot carry a transistor.

TSMC’s Super Power Rail (SPR) technology solves this by splitting the wafer into two distinct layers. The front side handles all signal and clock routing — pure data flow. The back side carries the power delivery network, with vertical backside contacts feeding each transistor’s source and drain directly. Think of it as an old office building that finally got a separate freight elevator.

Intel and Samsung are both reportedly researching or applying similar backside power approaches. But research and verified production-ready implementation are different things. TSMC is announcing a node with real silicon data.

Why Samsung should feel the floor shift

A Korean process industry expert told Hankyung — citing an insider familiar with TSMC operations — that the A16 completion could create what he called a “painful situation” for Samsung Foundry.

The expert was being charitable. What he meant, in effect, is this: Samsung has spent the better part of a decade trying to close the process gap with TSMC, and it has lost ground at every benchmark that matters to design teams. The A16 deployment — with backside power at a node below 2nm — extends that lead precisely where it hurts most.

Samsung foundry’s recent track record has not inspired confidence among its biggest customers. Yield problems at the 3-nanometer node, design wins that stalled mid-development, and a series of public setbacks have made AI chipmakers nervous about pinning their most ambitious products on a supplier that cannot reliably hit its own targets. Apple’s decision to move its latest custom silicon designs to TSMC’s 3-nanometer process was the loudest signal yet.

A16 arrives at the moment Samsung needs to prove it can execute. Instead, it confirms that TSMC is running ahead on technology the rest of the industry has only begun to sketch.

The AI chip buyer’s dilemma

This is not a story about process nodes in a vacuum. It is a story about who wins when the world’s most valuable companies need chips that do more with less power.

The leading AI accelerators — Nvidia’s upcoming Fermi generation, likely — consume tens of kilowatts per rack. Power efficiency is no longer a secondary spec. It is the bottleneck that determines whether a data center is economically viable at all. Every percentage point of improved power delivery translates directly into fewer cooling systems, fewer power supplies, fewer racks per megawatt.

Design houses choosing between TSMC’s A16 and Samsung’s nearest equivalent are not making an abstract technology decision. They are choosing between a node with verified backside-power data and a node without it.

This is the cycle that locks in foundry dominance. A customer chooses TSMC for its leading node, TSMC generates production experience and yield data, the data makes TSMC more attractive to the next customer, and the next customer’s design wins further strengthen TSMC’s ecosystem. Samsung is not losing this race because its engineers are inferior. It is losing because each passing generation makes the gap wider and the recovery harder.

The production timeline and what it means

TSMC is targeting production readiness for A16 in the second half of 2026, with volume ramp expected in the final quarter. The node is positioned as an intermediate step toward A14 — a 1.4-nanometer process that the company expects to enter full production in 2028.

The sequencing matters. A16 is not a final destination; it is the proving ground for backside power delivery at scale. The first customers to tape out on A16 will generate the yield data, the design kit maturity, and the manufacturing feedback that makes A14 viable. Whoever gets there first owns the next generation.

Samsung’s closest alternative — the equivalent of backside power plus sub-2nm performance — does not yet exist in production form. The company has announced its own GAA (gate-all-around) transistor roadmap, but the gap between roadmap announcement and high-volume manufacturing remains the most dangerous place for a foundry to occupy.

Who wins, who loses

TSMC consolidates its foundry position with a node that raises the barrier to entry for competitors and deepens its lock-in with AI and HPC customers. The company’s design ecosystem — the tape-out tools, the IP libraries, the foundry-supported design kits — becomes harder to leave.

AI chip designers — especially those building the next generation of training and inference accelerators — gain a real performance and efficiency edge. Their choices narrow, but the technology improves.

Nvidia, AMD, Google, and the other major fabless designers face a constrained set of options for their most power-sensitive products. TSMC is not just the preferred supplier; for many designs, it may become the only viable supplier at these nodes.

Samsung Foundry faces a widening credibility gap. Every quarter that A16 data circulates without Samsung offering a comparable node makes the gap harder to close. The company’s foundry strategy has always depended on winning design wins at leading nodes; A16 makes that dependency sharper and more painful.

Intel Foundry Services is also in this picture, though Intel’s backside-contact work has not yet reached the same public maturity. The technology is moving faster than any single company’s ability to catch it.

The longer arc

The A16 announcement is a process milestone, but it is also a market milestone. Backside power delivery is the architectural shift that defines the post-2nm era. Whoever commercializes it first controls the design ecosystem for the next decade of computing growth.

TSMC is not just shipping a faster chip. It is defining the floor under which the rest of the industry must operate. Samsung and Intel are now playing defense on terrain that TSMC helped create.

The pain for Samsung, as the Korean expert noted, is real. But the deeper story is about the structure of the foundry market itself — one that rewards execution speed with widening advantage, and punishes delays with structural irrelevance.