AI Just Designed a CPU and Booted Doom on It
GPT-5.6 Sol built a virtual RISC-V processor from logic gates and ran Doom on it — a leap from code generation into hardware design that could reshape how we think about autonomous engineering.
The CPU That Isn’t Real, Running the Game That Proves It Is
OpenAI’s GPT-5.6 Sol didn’t just write code this time. It designed a virtual CPU, wired together logic gates, registers, memory units, and an arithmetic logic unit, then booted Doom on top of it. The result appeared on X last week from Angel Bogado, an AI computing researcher and technical influencer who documented the experiment.
The processor, dubbed Codex-R32, runs inside the sandbox environment of Turing Complete — a computer science education game where players build processors from first principles. The model produced a working RISC-V architecture in RV32IM instruction set format. Doom was compiled via the PureDOOM C port and executed directly on the AI-designed silicon that exists only as logic gates in a browser-based simulator.
That’s the thing that matters. Not the frame rate. Not the performance. The fact that the model understood enough about digital logic and processor architecture to build something that could execute real binary code.
Beyond Code Generation Into System Design
For the past two years, the AI narrative has been dominated by coding assistants. GitHub Copilot. Claude. Codex. The story was always the same: AI writes software faster than humans. That story has exhausted itself. Every major model now does it. The interesting question is what comes next.
This demo points toward autonomous hardware design. Coding and hardware design are not the same problem. Software lives in a world of abstractions — compilers, runtime environments, virtual machines. Hardware sits closer to the physical constraints: timing, power, clock cycles, signal propagation. Getting a CPU to run correctly means the AI had to reason about those lower-level constraints without abstracting them away.
Bogado’s assessment was characteristically blunt: “This is insane.” Some commenters immediately asked if GPT-5.6 Sol could also run Crysis, the old meme benchmark for system capability. The model’s own answer was self-aware — it said it would need to create a GPU, add several gigabytes of RAM, and route circuits large enough to see from orbit. A deflection grounded in honest technical self-knowledge.
What This Means for the Semiconductor Industry
The immediate implication is modest. Codex-R32 doesn’t compete with Apple’s M-series or NVIDIA’s architectures. It runs Doom at a pace you wouldn’t describe as smooth. The Turing Complete sandbox is educational, not production-grade. A real EDA (electronic design automation) flow involves synthesis, placement and routing, timing closure, power analysis, and tape-out verification — none of which this demo touches.
But the direction matters more than the distance covered in a single sprint.
The semiconductor industry has been quietly automating parts of chip design for years. Tools from companies like Synopsys and Cadence already assist with register-transfer-level design and verification. What this demonstration shows is that foundation-model reasoning can now operate across domains that were previously siloed — natural language understanding meeting digital logic synthesis. An AI that can read a specification and produce a working processor is a different class of tool than one that autocompletes your Verilog.
This doesn’t replace human chip architects. But it does lower the barrier to entry for prototyping and educational use, and it points toward a future where the front end of hardware development — specification, architecture exploration, early RTL generation — becomes increasingly assisted by capable models.
The Significance Is Methodological, Not Spectacular
There are several reasons not to overread this moment. The simulation environment imposes hard limits. The CPU has no floating-point unit beyond basic ALU operations. There’s no cache hierarchy, no out-of-order execution, no modern pipeline features. The fact that Doom runs on it is impressive for a proof of concept. It’s not a chip that ships.
But the methodological shift is real. Earlier AI coding demos demonstrated pattern completion and syntax production. This one required the model to maintain state across multiple levels of abstraction simultaneously — understanding both the high-level program and the low-level gate arrangements that execute it. That’s systems thinking, not just pattern matching.
The Turing Complete sandbox is also a constraint that works in the model’s favor. It operates within a known, simplified architecture space. Generalizing this to full chip design would require handling far more ambiguity, far more failure modes, and physical realities the sandbox ignores entirely.
Who Wins, Who Loses
The winners here are educational platforms and anyone doing hardware prototyping outside mainstream silicon houses. Turing Complete and similar tools become dramatically more useful when students can ask an AI to demonstrate a working design rather than just describe one. Professional FPGA developers and RISC-V community builders gain new workflows for rapid iteration.
The losers are less clear-cut. No jobs disappear from this single demonstration. But the trajectory favors organizations that can integrate capable models into their design review processes. Firms that treat AI as a coding sidekick rather than a design partner may find themselves falling behind on the architecture side first, before the EDA tools catch up.
What Comes Next
Bogado and other observers have already pointed toward the next obvious question: can the model design its own GPU? Can it scale up to a processor with pipeline stages, branch prediction, maybe even a simple cache? Can it produce actual synthesizable RTL instead of a simulator-level description?
The model itself answered honestly. It needs more memory, more transistors, and presumably another round of architectural reasoning. The jump from a toy CPU to a usable processor is large but not impossible — it’s the same order of magnitude as the jump from writing simple scripts to building compilers.
What’s significant about this moment isn’t that AI can now design hardware. It’s that the boundary between what AI can help with has moved past code into systems. The industry’s next competitive question isn’t whether models can generate RTL. It’s whether they can generate RTL that survives timing closure.