Beyond HBM4E: How Korea's Memory Giants Are Rewiring AI

The HBM4E Baseline Is Already Here

Samsung and SK Hynix have both shipped HBM4E samples to customers. Samsung announced its 12-stack 48 GB product in May; SK Hynix followed in June. At SEDEX 2026, held at COEX in Seoul’s Gangnam district from October 14–16, neither company treated HBM4E as the finish line. They used it as a launchpad.

The numbers are instructive. Samsung’s HBM4E pairs a 6th-generation 1c DRAM die with a 4 nm foundry base die, pushing per-pin speed from 14 Gbps to 16 Gbps — a gain of more than 20 percent. Maximum bandwidth reaches 3.6 terabytes per second. SK Hynix’s version matches that 16 Gbps target while claiming a 20 percent improvement in energy efficiency over HBM4. Both are meaningful upgrades. But the real story at SEDEX was what sits beyond them.

Two Different Designs for the Same Problem

The bottleneck in AI is no longer just how fast memory can move data. It is how far that data has to travel.

Samsung’s answer is zHBM — a 3D structure that stacks memory directly on top of the GPU rather than beside it on the substrate. The physical distance between compute and storage shrinks dramatically. Data moves faster. Power drops. Samsung also displayed LPDDR-PIM, which performs computation inside the memory itself, reducing the number of round trips to the processor. Alongside these, a 3D NAND solution called zNAND-O was shown, aimed at edge AI devices where power and space are even tighter constraints.

SK Hynix took a different path with HBF — high-bandwidth flash. The idea is to bridge the gap between HBM’s raw speed and NAND’s density. HBF promises roughly ten times the storage capacity of conventional HBM while maintaining high throughput. In practice, that means a system could hold far more of a large language model’s weights in fast-access memory during inference, rather than shuffling data between layers of hierarchy.

These are not incremental improvements. They represent diverging philosophies about how AI infrastructure should be organized. Samsung is pushing toward vertical integration — memory on compute, compute inside memory. SK Hynix is pushing toward architectural layering — a new memory tier between HBM and storage that changes the shape of the whole server.

The Packaging War Is the Real Competition

HBM4E alone would not require the kind of foundry and packaging capabilities Samsung and SK Hynix are now displaying side by side. The base die that sits under the stacked DRAM — the part that handles power delivery, signaling, and thermal management — is increasingly a design challenge as much as a manufacturing one.

Samsung showcased a 4 nm base die for HBM4E, a 2 nm gate-all-around wafer, and two advanced packaging approaches: 2.3D Cube-E and 3D Cube-H. The message is clear. Samsung wants to sell memory, logic design, and packaging as a single package — literally. Customers building custom AI accelerators will increasingly need a partner who understands all three.

SK Hynix made a parallel move, displaying a wafer bearing Jensen Huang’s signature for Nvidia’s upcoming Vera Rubin superchip platform. That is a credibility signal as much as a product announcement. SK Hynix is saying: we are embedded in the world’s most important AI platform, and our roadmap extends beyond current products.

What This Means for AI Inference

The shift from training to inference is the structural change driving all of this. Training requires massive bandwidth for a short time. Inference is a continuous, latency-sensitive workload that runs against models that keep growing. Every additional parameter pushes the memory wall harder.

A model that fits entirely in HBM during inference avoids the expensive DRAM-to-flash data movement that dominates power consumption on today’s servers. HBF, if it delivers on its promise, could move a significant portion of model weights into that fast tier. zHBM could make that tier smaller and more efficient by placing it closer to the processor. Both approaches target the same problem from different angles.

The OCP Summit earlier this year added technical weight to the CXL-memory direction that SK Hynix’s HBF concept aligns with. CXL allows memory to be pooled and distributed across servers — a fundamentally different architecture from the current model where each GPU carries its own HBM stack. If CXL-based memory pools prove viable at scale, the players who understand both the memory hierarchy and the protocol stack gain a structural advantage.

Who Wins, Who Loses

The winners in this phase are the companies that can deliver these architectures at volume. Samsung and SK Hynix have the foundry relationships, the packaging know-how, and the customer access. Nvidia, AMD, and the major cloud providers are the customers watching closely.

The loser today is the status quo. The layered memory hierarchy — HBM next to the GPU, DRAM below, SSD further down — is being questioned by both Korean manufacturers simultaneously. If either zHBM or HBF proves commercially viable first, it changes the design rules for every AI server built over the next five years.

There is a caveat. Both zHBM and HBF remain in development. Samsung’s zHBM prototype was displayed as a model. SK Hynix’s An Hyun described HBF and 3D stacked DRAM as part of a roadmap toward 2030, when he expects AI infrastructure performance to grow roughly twentyfold from today’s levels. Neither technology has a shipping date. Customer adoption is unconfirmed.

What Comes Next

The race is no longer just about who can stack the most DRAM dies or hit the highest Gbps. It is about who can redefine the memory architecture of AI systems before the next generation of models makes the current design economically unsustainable. Samsung is betting on proximity and integration. SK Hynix is betting on hierarchy and capacity. Both are reasonable bets. The one that lands first will set the standard.

SEDEX 2026 showed both companies are serious about playing beyond memory. That is the signal worth watching.