Samsung Bets the Chip House on ASML's Next-Gen Tool

Samsung Is Running a Five-Year Gap Race

Samsung Electronics is betting its DRAM future on a single change in the toolchain — switching from 6-inch to 12-inch photomasks for high-NA EUV lithography. The company confirmed its entry into ASML’s consortium developing the new mask standard on May 8, alongside TSMC and Intel. SK Hynix is reviewing participation. Samsung alone, however, has committed to a 2028 mass-production target for DRAM using the technology. That timeline is roughly five years ahead of TSMC, which says it won’t begin pilot lines until 2031 and won’t reach volume production until 2033.

The difference matters more than it might seem at first glance. In memory chips, process nodes shift faster than in logic. A DRAM player that can量产 high-NA EUV–processed memory by 2028 will have an extended window to define yield curves, refine design rules, and lock in customers before the rest of the field even owns the equipment.

The Mask Is the Bottleneck Now

The reason for the mask-size change is straightforward but significant. High-NA EUV machines, which cost roughly $400 million each and feature a numerical aperture of 0.55 versus the 0.33 of earlier generation tools, expose circuit patterns at roughly 8-nanometer resolution. The catch is that the larger NA lens shrinks the usable exposure area by about half when using the existing 6-inch masks. Manufacturers are forced into “die stitching” — exposing adjacent die separately and attempting to align them during the etch process. Stitching adds complexity, slows throughput, and raises defect rates. None of those things are acceptable when you’re trying to print billions of transistors for AI accelerators and data-center memory.

A 12-inch mask doubles the exposure area in a single step. Die stitching becomes unnecessary. Throughput climbs. Unit economics improve. The move is not incremental — it is the difference between a lab demonstration and a factory floor that can ship product.

Samsung is moving aggressively on this front. The company imported its first high-NA EUV system into South Korea in March 2024, months before any competitor. It is now using that equipment to validate process conditions and yield targets internally while simultaneously securing early access to the 12-inch mask standard through the ASML consortium. The strategy is to have production-ready DRAM designs and process flows in hand when the masks are available, rather than discovering both problems at once like later entrants will.

SK Hynix Is in a Tight Spot

SK Hynix announced it also plans to introduce high-NA EUV into DRAM production by 2028. On paper, the timelines match. In practice, Samsung’s early equipment import and its confirmed seat at the 12-inch mask table give it a tangible advantage in execution speed. If SK Hynix’s consortium participation review delays its access to the new mask standard, Samsung could widen the gap precisely where it counts — in yield and cost per chip.

This is not merely about being first. It is about who defines the process window first. Memory manufacturers that nail yield on a new lithography node early capture the premium segment of the market — high-bandwidth memory for AI training, low-latency server DRAM, the products that command the highest margins in any cycle. Whoever gets there first sets the reference design that the rest of the industry follows.

TSMC Is Playing a Different Game

TSMC’s later timeline — pilot in 2031, volume in 2033 — reflects a different prioritization. TSMC is focusing high-NA EUV capacity on advanced logic nodes, not memory. That does not make Samsung’s move any less consequential. Memory and logic are increasingly converging in the AI era. HBM (high-bandwidth memory) is essentially logic-tier circuitry stacked on top of DRAM dies, and the same high-NA tools and mask standards will serve both. Samsung’s head start in memory process development creates spill-over advantages for its logic business as well.

Intel, also a consortium member, faces its own execution challenges in memory and is unlikely to contest Samsung’s DRAM lead on these grounds. The real competition for Samsung is SK Hynix, not TSMC.

What Changes Next

The immediate implication is a reshuffling of who controls the next memory cycle’s margin distribution. Samsung’s strategy is clear: use the toolchain transition as a lever to leapfrog its closest rival in the one segment where it has historically lagged — DRAM process leadership. If the 2028 target holds, Samsung becomes the first memory maker to ship products made with the full high-NA EUV + 12-inch mask combination. That sets the process benchmark.

The global supply chain impact is smaller than the competitive story but still real. ASML’s 12-inch mask production capacity will be constrained initially. TSMC, Samsung, and potentially Intel will be competing for allocation. Any delay in mask supply could compress Samsung’s five-year advantage into something closer to three. That outcome would benefit SK Hynix disproportionately — it is the only competitor with the process capability to close the gap quickly if the mask bottleneck eases.

Samsung’s commitment signals confidence that the mask transition will proceed on its timeline. It is a bold read of the toolchain landscape, and one that will determine whether Samsung reclaims the memory lead it lost during the previous DRAM cycle — or falls further behind if execution slips.